Certain semiconductor manufacturing processes allow for the usage of stacked vias. Such physical structures usually require the definition of specific rules between the different elements of the stack. Typical examples of such rules include requirements on the way shapes of cuts are stacked within a via and the minimal area rules for the intermediate routing layers of the via for the intermediate levels in the stack.
Automated place and route tools can fulfill these requirements by selecting one solution in the domain spaces of the different parameter combinations. However, in the custom circuit design area, it is not uncommon for the physical layout designers to want to control each individual parameters of the stack. There are two conventional implementations. First is a parameterized cell (PCell) approach, where an “instance” of the via is created, while a design language is used to manage the creation of the shapes within the instance master. Second is a manual approach, where the designer layouts a stack of vias and crafts each via individually by tuning the parameters of the via.
FIG. 1 illustrates a stacked via. This stacked via 100 has four layers, going from bottom layer 110 to a first intermediate layer 120, to a second intermediate layer 130 and a top layer 140. There is also an array of 2×2 cuts between each layer 115, 125, 135. Array 115 is in between bottom layer 110 and first intermediate layer 120. Array 125 is between the first intermediate layer 120 and the second intermediate layer 130. Array 135 is located between the second intermediate layer 130 and the top layer 140.
FIG. 2 illustrates a stacked via with and extended intermediate layer. This stacked via 200 is similar to the stacked via of FIG. 1. It also has four layers, going from bottom layer to top layer 210, 220, 230, 240, with an array of 2×2 cuts between each layer 215, 225, 235. Intermediate layer 220 has a process rule requiring a minimum area, which is larger than what the regular cut overlap rule defines for this specific layer. In such case, the user must adjust the area to be larger. Stretching one edge of the intermediate layer 220 can do this. Routing tools use pre-defined combination of MAR via that stretch in the direction perpendicular to the routing direction for that layer.
FIG. 3 illustrates a stacked via that precludes the overlapping of cuts. This stacked via 300 is similar to the stacked via of FIG. 1. It also has 4 layers, going from bottom layer to top layer 310, 320, 330, 340, with an alternate array of cuts between each layer 315, 325, and 335. Each layer includes 2 cuts, and the cuts alternate such that successive cut layers have cuts that are rotated 90 degrees. In other words, no cuts are located immediately above or below another cut.
FIG. 4 illustrates another stacked via that precludes the overlapping of cuts. This stacked via 400 is similar to the stacked via of FIG. 3. It also has 4 layers, going from bottom layer to top layer 410, 420, 430, 440, with an alternate array of cuts between each layer 415, 425, and 435. In FIG. 4, the cut layers are shifted 90 degrees with respect to the top layer 440 and bottom layer 410.
The stacked vias of FIGS. 3 and 4 result from process rules precluding the overlap of cuts in the stacked via. Stacked vias of FIGS. 3 and 4 are useful when design rules violate the design in FIG. 2 above. There are several different solutions that can be created by the custom designers, some of which may be allowable by the rules in some processes while others may not. Alternate arrays of FIGS. 3 and 4 are common choices, but some processes also allow straddling via cuts. Some are dictated by the process rules, others depend on the surrounding shapes, or considerations understood only by the person creating the layout.
In a PCell approach, an “instance” of a via is created. The PCell may be written for OpenAccess (OA) in a non-proprietary language such as C++ and/or Python. A collection of parameters associated with the PCell allows the designer to control the intermediate plates and cuts, while the PCell coder made sure that the process rule are enforced in the actual code. In a manual approach, the designer provides layouts including stack of vias and crafts each of them individually by tuning the parameters of the via instance. These two approaches have many drawbacks.
First, the PCell approach is not “interoperable”. The stack only exists in the tool virtual memory (VM) space, which is evaluated by the design language used to describe the PCell super-master. The stack is embedded within a level of hierarchy. This embedding prevents the routing tools from being able to interact or connect with the intermediate levels of the stack.
Furthermore, in OA, the PCell approach does not allow parameterization of the top and bottom layers of the stack. In OA, although it is possible to “bind” a PCell supermaster to a via definition, by construction, an OA via definition requires a fixed top and bottom layers. The PCell master is linked to a customViaDef in the OpenAccess technology database, defining the two predefined top and bottom access point into the via object. Such PCell master does not have parameterized top and bottom layer names.
Even if the PCell itself contains all the intermediate interconnect shapes, these are not visible to the routing applications in OpenAccess.
customViaDef( (viaDefName topLayer bottomLayer lib cell view))
FIG. 5 illustrates a stacked via in OpenAccess (OA) using the PCell approach. This stacked via 500 has 4 layers, going from bottom layer to top layer 510, 520, 530, 540, with an alternate array of cuts between each layer 515, 525, 535. This structure is stored together as a Pcell.
On OA, the PCell approach does not allow parameterization of the stack layers 520, 530. In OA, although it is possible to “bind” a PCell supermaster to a via definition, by construction, an OA via definition requires a fixed top 540 and bottom 510 layers.
customViaDef( (viaDefName topLayer bottomLayer lib cell view))
Second, the manual approach is not user friendly, and requires the end user to manually create each individual levels of the stack. The user has to remember all the interlevel rules. There is no notion for visualizing the stacked via as a whole. It has to be created by all discrete objects using editors. Therefore, the manual approach can not provide assistance in recognizing that assemblage as a special object.